PYNQ: Python Productivity for Zynq

I was a developer for the PYNQ project from May – January 2018, and added support for the Zynq Ultrascale+ devices like the Ultra96 board from Avnet. Below is a selection of PYNQ related projects that I have released since: RISC-V on PYNQ, PYNQ+HLS, PYNQ-Copter


PYNQ is an open-source project from Xilinx® that makes it easier to use Xilinx platforms.

The main goal of PYNQPython Productivity for Zynq, is to make it easier for designers of embedded systems to exploit the unique benefits of Xilinx devices in their applications. Specifically, PYNQ enables architects, engineers and programmers who design embedded systems to use Zynq devices, without having to use ASIC-style design tools to design programmable logic circuits.

Using the Python language and libraries, designers can exploit the benefits of programmable logic and microprocessors to build more capable and exciting electronic systems.

PYNQ can be used with Zynq, Zynq UltraScale+, Zynq RFSoC, Alveo accelerator boards and AWS-F1.


The RISC-V specification is a highly flexible specification for low-cost processors. The RISC-V ISA is royalty free, vendor agnostic, easily portable between development environments, and highly flexible to match the demands of an application. These characteristics make RISC-V a natural ISA choice for an FPGA soft processor and this has led to widespread adoption in academia and industry. However, the sheer number of RISC-V projects can be daunting for potential users.

This project is a tool for exploring RISC-V projects using PYNQ is a deployment platform. The GitHub repository provides instructions for instantiating, connecting, and compiling RISC-V cores so that they are recognized by the PYNQ framework.

Once RISC-V Cores are recognized by PYNQ, users can compile and run C, C++, and assembly on the RISC-V processors that they have compiled from Jupyter Notebooks (Normally a python interface!).

A simple example of compiling and running C++ and then RISC-V assembly is shown below:


Similar to RISC-V on PYNQ, this project is a tutorial for deploying High-Level Synthesis Cores on PYNQ. The GitHub repository provides instructions for instantiating, connecting, and compiling HLS cores so that they are recognized by the PYNQ framework. This project was the foundation for the lab sections in CSE 237C: Validation and Prototyping of Embedded Systems and WES 237C: Hardware for Embedded Systems at UCSD. The course materials can be found here.

The notebooks in the repository guide users through interfacing two common types of HLS cores: Streaming, and Shared Memory. The streaming tutorial, demonstrating a 1-D filter applied to a photo is shown below:


FPGAs are a computing platform that excel in performing signal processing, control, networking, and security in a high performance and power efficient manner. This makes FPGAs attractive for unmanned aerial vehicles (UAVs) especially as they require smaller payloads and are processing multiple high data rate input sources (e.g. cameras, lidar, radar, gyroscopes, accelerometers). Unfortunately, FPGAs are notoriously difficult to program and they require significant hardware design expertise.

However, there are newly released design tools aimed at making FPGAs easier to use, which drove the initial hypothesis for this paper: could three undergraduates program an FPGA to control a UAV in 10 weeks? The result of the experiment is PynqCopter – an open source control system implemented on an FPGA. We created and tested a UAV overlay which is able to run multiple computations in parallel, allowing for the ability to process high amounts of data at runtime.

See a video of the PYNQ-Copter’s maiden flight below: